VHDL codes in an ALU deisgn (Supporting Floating Point )
What is VHDL
VHDL is the Verilog Hardware Description Languatge.
Synopsis is the software to analyze digital logic of VHDL.
How to use Synopsis? ( ps file)
FPU design
The Floating point divider is based on the Radix-2 logic.
All files are located in /vhdl directory
A File list:
tb.vhd (
test_bench)
fp_divider.vhd
( main file of floating point divider)
add_g.vhd
fa.vhd
mux2to1_n.vhd (multiplexer)
mux4to1_n.vhd
mux1, mux24, mux234_4.vhd...
subtractor_8bit.vhd
bshift.vhd
fp_divider.vhd
test_bshift.vhd
csa.vhd
frac_preshift.vhd
ofc.vhd ( on-the-fly
converter)
digit_sel.vhd
digit_q.vhd
ins_g.vhd
reg_n.vhd (n-bit register)
encoder23.vhd
lzd.vhd
srt_div_data.vhd
srt_div.vhd
After the Synthesis with Synopsis software,
the diagram of a FPU (floating pointer divider unit) will be
generated. There are another three associated diagrams.
- diagram plot 1
- diagram plot 2
- diagram plot 3
Design Description and Simulation Results
Another suite of design diagrams (plot0.ps
plot1.ps plot2.ps
sim1.ps sim2.ps
)
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Design of a floating point divider:
---------------------------------------------------------------
by ZHIBIN WU
For dividing operation of floating point numbers,
sign, exponent and fraction part has to be handled individually.
Because IEEE 754 format (single) of floating point format is adopted
here.
Thus, each operand has a 8-bit exponent and 23-bit fraction and 1-bit
sign.
To calculate the result,
The calculation is composed of
1. 1 bit XOR the signs of two operand.
2. 8 bit subtraction of the exponents of two operands.
3. 23 bit division is to be performed to generate the fraction result.
This is the basic three steps. Some accessories are also needed for
shift operation and additional 8 bit adder/subtractor to adjust the
bias of exponent part in IEEE 754 format.
Next, I focus on the design of the most complicate part as the 23-bit
division of the floating point divider.
Basically, the method for the divide operation is
classified in two classes:1
1. Look-up table to find a reciprocal of the divider, and then use
multiplication to finalize the divide operation.
2. Recursive Add/Subtract operation.
Here, I use a method of the second class, and the method's name is
SRT radix-2 algorithm.
This algorithm requires that the divider Q is between [0.5,1),
and the divident X is less than Q.
This demand could be easily satisfied with the normalization of IEEE 754
format. Because each fraction part of the floating point number is
within
the range of [1,2), if the divident is shift right for 2-bit. Then it
will
lie in the range of [ 0.25,0.5). And if the divider is shift right for
1 bit, then it will lie within the range of [0.5,1). Thus, the
requirement
for the range is met with only shift operations. Remember that the
divident
and divider is shifted with different bits. The final result should be
normalized to get the correct value.
TO design the SRT radix-2 algorithm for division, a sequential logic is
used
to recursively subtract the divider D from the divident X.
The major part of the design is a 24 bit full adder/subtrator and a 24
bit register to save the partial remainders in the algorithm.
Each subtraction is performed within one clock. Thus, it totally needs
24 clocks to get the final result (Quotient).
This can be seen by the waveform of SYNOPSIS VHDL debugger.
To facilitate the subtraction operation, three multiplexer is used to
supply
correct inputs and carry-in to the adder/subtractor.
Also, beside clock signal, an "init" signal should be supplied by
Control
parts of the CPU to initialize the divide operation.
As the division is made with a sequential logic, the final result is
generated by a on-the-fly converter (it is basically a
serial-to-parallet
converter).
The simulation waveform and block diagram of the fraction (mantissa)
division
is attached.
November 5
Zhibin Wu
--------------------------------------------------------------------------
Transister
Level Scheme and Simulation results
-------------------------------------------------------------------------
For floating point divider:
An abstraction of the
divider show that the divider is actually
a recursive-subtractor
(adder), whihc is controlled by clock signal
Within each clock cycle, the
adder/subtractor performs a 24-bit adder
operation for the shifted
remainder and divider.
After 23 clocks, we could
get final results. ( becasue the fraction
part of IEEE 754 format is
only 23 bits). however, we need 24-bits adder
to decide each bit of
Quotient.
The most basic unit of the
divider is of four type of basic cells:
1. 1-bit full adder
2. A positive-edge
triggered register
3. A 2 to 1 multiplexer
4. A 4 to 1 multiplexer
The purpose for the register
is to store and shift the remainder.
The purpose of the 2-to-1
multiplexer is to select between remainder
and initial divident.
The purpose of the 4-to-1
multiplexer is to select between d, -d, and
zero. d represents divider.
First attached are design of
basic cell as adder, regisrter and
multiplxer and their
simulation results. As the multiplexer is quite a
standard desig, i
don't simulate it.
Then, I symbolize those
basic cells and design a 24-bit recursive
adder, which is the core
part of the floating point divider.
The diagram is attached as an top-level diagram whcih is
composed of
basic adders, inverters,
registers and multiplexers.
Finally, is the simulation
results of this top-level design.
In the simulation,
The A is assigned as "0000
0000 0000 0000 0000 0000"
The B is assigned as "0101
0101 0101 0001 0101 0100"
The init and clock signals
are also present.
The first simulation plot
shows the situation when a wrong "INIT"
signal is given, which means
after 1st clock, the INIT keeps high,
and each time, the adder
performs same add operation with same
operand. Thus all S signals
keeps same.
The second simulation plot
shows the correct situation. I can see
that the output of the S
signals are varing according to the clock.
It proves that each time,
there is a shifted S outputs are re-feed
into the adder/subtractor.
Thus, the final change will stop at 96us
at last ( with the 4u
clock). Also, after the 96us, I need to change
INIT signal as high again to
begin a new divide operation.
However, as I only simulate
once in this test, I keep the INIT
signla low till 100us.
The significance of the
simulation results is that gives the answer
of critical timing issues
and prove that the recursive
adder/subtractot can work
corretly with the clock phase and init
signal.
Zhibin Wu
Nov. 11. 2002