Dr. Zoran Miljanic
WINLAB
Rutgers University
SHORT
BIOGRAPHY
Zoran
Miljanic has more
than 20 years of industry experience in computer and communications technology,
with technical and management roles of increasing responsibility in IBM T.J
Watson, Bell Labs, NEC Labs, Network Machines, Velio Communications and
Conexant Systems. Zoran is co inventor of the classical Foschini-Miljanic
algorithm for power control based distributed channel allocation in cellular
wireless networks. He was the lead architect for the number of systems and
semiconductor products: gigabit switches, multimedia communications platform,
video server, and network processors. He assembled and managed multi site teams
at USA eastern and western costs, Asia, and Eastern Europe. He holds number of
patents and has published numerous publications in leading journals and
conferences.
Zoran has organized and chaired international broadband conferences workshops and reviewed numerous papers for the leading journals and conferences. He is the founder and president of Technology Networking International LLC, the company focusing on the promotion of broadband communication industry in the emerging markets of Eurasia. He is also research professor at Rutgers University Wireless Information Network Laboratory (WINLAB) leading the effort on the design of new cognitive radio platforms for the next generation wireless networks.
PROFESSIONAL ACCOMPLISHMENTS AND EXPERTISE
·
Invented the Virtual Flow Pipelining (VFP), new
paradigm for programmable communication processing. Architected and lead the
proof of concept design of VFP based programmable wireless protocol processing
platform at Rutgers WINLAB (WiNC2R)
·
Architecture and design of wire speed OC-12 rate
fully programmable network processor. Recognized need and benefits for low
latency I/O, zero cycle context switching and multithreaded architecture for
data plane processing
·
Architecture and design of Multimedia
Communication and Computing Platform – one of the first R&D projects in the
industry that demonstrated the benefits of network centric computing paradigm
·
Architecture and design of one of the first
gigabit per second switches with built in lossles end-to-end flow control and
self reconfiguration
·
Coauthored seminal paper about power control
based channel assignment in cellular networks, now known as Foschini-Miljanic
Algorithm
·
Established successfully complete semiconductor
device functional verification flow in fables semiconductor company, lead multi
site teams and successfully completed multiple projects with no functional
flows
·
Ability to grasp the cutting accomplishments
edge problems and come up with architectural innovations in the high-speed
communications switching and processing technology.
·
Track record in building and leading
geographically dispersed teams for hardware board design, ASIC standard
cell/FPGA design and embedded software development.
·
Semiconductor components pre-silicon functional
verification: self-checking random and directed functional verification
methodology, infrastructures set and test bench design. Functional and code
coverage techniques and practices.
·
System on a Chip (SoC): hardware/software
co-design and co-simulation, SoC bus evaluation, analysis and integration (IBM
Core Connect, ARM AMBA, SONICS), IP core selection and integration
considerations.
·
ASIC Design: architecture specification,
micro-architecture design, functional verification and chip integration
methodology.
·
Communications protocols ATM, IP routing/switching,
MPLS, synchronous protocols/services; innovations in lossles flow control for
asynchronous networks, distributed wireless channel allocation, and distributed
power control protocols.
·
Architecture and design of high speed networking
devices from systems to components: Gigabit switches, ATM switches/servers,
inter-processor bus switches, scheduler, buffer management, high speed memory
interface, memory management and controller design, Utopia 2/POS interfaces.
·
CPU and Network Processor modeling, analysis and
design. Wire speed processing architecture, VLIW processor architecture and
design, compiler and ISS porting and integration methodology, performance
modeling and evaluation.
·
System simulation and analysis. Modeling in
C/C++/VHDL/SystemC from behavioral to cycle accurate level in quite diverse
areas: wireless systems, distributed computing, CPU performance models,
communications switches and network processors. Early adaptor of SystemC as in
the golden behavioral model and full chip verification design.
EDUCATION
1993, Ph.D., Electrical and Computer Engineering, Rutgers University, New Jersey1988, M.Sc., Computer Engineering, University of Belgrade, Yugoslavia
1984, B.Sc., Electrical Engineering, University of Belgrade, Yugoslavia